Programme Category
Programme Name
Programme Description
Το πρόγραμμα Κοινή Επιχείρηση Chips (Chips JU) είναι μια πρωτοποριακή πρωτοβουλία που δεσμεύεται να καταλύσει τις δυνατότητες έρευνας, ανάπτυξης και παραγωγής σε όλη την Ευρώπη. Σε αυτήν την ενότητα, εμβαθύνουμε στις βασικές πτυχές της Chips JU και στην αποστολή της ώστε να διαμορφώσει το μέλλον των ημιαγωγών της Ευρωπαϊκής Ένωσης.
Η Κοινή Επιχείρηση Chips (Chips JU) υποστηρίζει την έρευνα, την ανάπτυξη, την καινοτομία και τις μελλοντικές παραγωγικές ικανότητες στο ευρωπαϊκό οικοσύστημα ημιαγωγών.
Identifier Code
Call
Summary
The proposed accelerator should address all levels of the key technological steps required to bring sSOI substrates to industrial scale:
- Development of industrial-grade sSOI substrates will focus on achieving low defect density, crucial for enhancing electron mobility and ensuring high-performance FD-SOI devices at the 7 nm node. This will involve refining strain engineering techniques, particularly to introduce a uniform global strain that can balance the performance for strained NMOS and relaxed PMOS transistors.
- Ensure compatibility with existing semiconductor manufacturing, the accelerator will refine process integration and optimisation. This includes improving epitaxial growth, wafer bonding, and defect reduction techniques to meet the requirements of advanced FD-SOI production processes.
Finally, the accelerator will promote collaboration across the semiconductor ecosystem, working with other pilot lines, as well as connecting to the design platform and competence centres, among others
Detailed Call Description
The proposed accelerator shall be established with all the necessary equipment and facilities, and will target the following main objectives:
- Develop industrial-grade sSOI substrates with reduced defect density to improve electron mobility and overall device performance. These substrates should be capable of addressing the market entry of 7nm FD-SOI expected by 2030.
- Develop scalable and cost-effective manufacturing processes, ensuring compatibility with current industrial standards and promoting widespread adoption.
- Demonstrate the feasibility of integrating strained NMOS and relaxed PMOS areas, balancing the performance of both transistors.
- Accelerate the transition from R&D to industrial-scale production by providing a pre-industrial infrastructure capable of producing several thousand wafers per year.
- Develop demonstrators to validate the benefits of sSOI-based FD-SOI over competing FinFET technologies, particularly in terms of improved RF performance, lower noise, and reduced power consumption.
- Enable open access to Process Design Kits (PDKs) and design building blocks to foster the differentiation of FD-SOI technology, including stress and relaxation design elements.
- Enable early-stage design and system-level integration of sSOI substrates through MultiProject Wafer (MPW) runs, allowing timely validation of substrate performance in real-world applications.
Call Total Budget
Financing percentage by EU or other bodies / Level of Subsidy or Loan
Reimbursement rates as percentages of the eligible cost according to DIGITAL
25% For profit organisation but not an SME
35%SME (for profit SME)
35% University/Other (not for profit)
Expected EU contribution per project: between €1.000.000 and €3.000.000.
Thematic Categories
- Information and Communication Technologies
- Information Technology
- Research, Technological Development and Innovation
Eligibility for Participation
- Businesses
- Educational Institutions
- Large Enterprises
- Legal Entities
- NGOs
- Other Beneficiaries
- Private Bodies
- Researchers/Research Centers/Institutions
- Semi-governmental organisations
- Small and Medium Enterprises (SMEs)
- State-owned Enterprises
Eligibility For Participation Notes
Admissibility conditions are described in Annex 2 “General DIGITAL EUROPE PROGRAMME conditions” of the WP General Annexes 2023-2027.
There are specific eligibility criteria relevant to each Participating State listed in the Chips Joint Undertaking (Chips JU) Work Programme 2023-2027.
For detailed information about the eligibility conditions for each call, please visit the Chips Joint Undertaking (Chips JU) Work Programme 2023-2027.
For the partners of a Participating State that coordinates grants, specific rules may apply regarding the eligibility to national funding.
For more details, please refer to the Governing Board Decision on the evaluation and selection procedures related to the calls launched by the Chips JU (GB 2024.71).